The present invention relates to an analog-to-digital (A/D) conversion method, an A/D converter, a semiconductor device, having a plurality of unit elements, for detecting a distribution of a physical quantity, and an electronic apparatus. In particular, the present invention relates to a technique for converting an analog output into digital data in a semiconductor device and an electronic apparatus, in which a plurality of unit elements responsive to an electromagnetic wave inputted from the outside, such as light or radiation rays, converts the input electromagnetic wave into the distribution of the physical quantity as an electrical signal, and the electrical signal is selectively read through address control.
Semiconductor devices for detecting a distribution of physical quantities are widely used. Such semiconductor device includes unit elements (such as pixels) responsive to an electromagnetic wave, such as light or radiation rays, arranged in a line or a matrix.
For example, a charge-coupled device (CCD), a metal-oxide semiconductor (MOS) device, and a complementary metal-oxide semiconductor (CMOS) device, each device for detecting light (one type of the electromagnetic waves) as a physical quantity, are typically used in the video equipment field. After being converted into an electrical signal by a unit element (pixel in the solid-state image pickup device), these devices read the distribution of the physical quantity.
Some solid-state image pickup devices have pixels, each pixel including amplifying solid-state image pickup element (active pixel sensor or also referred to as gain cell). The active pixel sensor includes a drive transistor for generating a pixel signal in response to a signal charge generated in a charge generator. Many of the CMOS solid-state image pickup devices have such a structure.
To read the pixel signal in the amplifying solid-state image pickup device, address control is performed on a pixel area having a plurality of pixels so that a signal is read from any individual pixel. The amplifying solid-state image pickup device is thus an address control type solid-state image pickup device.
The amplifying solid-state image pickup device, which is one type of X-Y addressing solid-state image pickup devices having a matrix of unit pixels, is MOS structured with a MOS transistor in each pixel to impart amplification capability to the pixel. More specifically, an active element amplifies a signal charge (photoelectron) stored in a photodiode as a photoelectric conversion element, and the amplified signal is read.
In such an X-Y addressing solid-state image pickup device, a large number of pixel transistors are arranged in a two-dimensional matrix to form a pixel area. The storage of signal charge starts in the pixels on a per line (row) basis or individually. A current signal or a voltage signal responsive to the stored signal charge is successively read by addressing. In the MOS types (including the CMOS type), in one of the typical address controls, one row of pixels is concurrently accessed and a pixel signal on a per row basis is read from the pixel area.
An analog pixel signal read from the pixel area is converted into digital data by an analog-to-digital (A/D) converter as necessary. Since the output pixel signal is a mixture of a signal component and a reset component, an effective signal component needs to be extracted by taking a difference between a signal voltage corresponding to the reset component and a signal voltage corresponding to the signal component.
The same is true when the analog pixel signal is converted to the digital signal. The difference component between the signal voltage corresponding to the resent component and the signal voltage corresponding to the signal component need to be converted into digital data. To this end, a variety of A/D conversion mechanisms have been proposed in the following patent documents and non-patent documents:
Patent document 1: Japanese Unexamined Patent Application Publication No. 11-331883;
Non-patent document 1: W. Yang et. al., “An Integrated 800.times.600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999;
Non-patent document 2: Kazuya YONEMOTO, “CCD/CMO Image Sensor no kiso to ouyo”, CQ Publishing Co., Ltd, first edition p 201-203, Aug. 10, 2003;
Non-patent document 3: Toshifumi IMAMURA, and Yoshiko YAMAMOTO, “3. Kosoku kinou CMOS image sensor no kenkyu”, Internet
<URL:http://www.sankaken.grjp/project/iwataPJ/report/h12/h12in-dex.html>
on-line searched Mar. 15, 2004;
Non-patent document 4: Toshifumi IMAMURA, Yoshiko YAMAMOTO, and Naoya HASEGAWA “3. Koshoku kinou CMOS image sensor no kenkyu”, Internet
<URL:http://www.sankaken.grjp/project/iwataPj/report/h12/h14ind-ex.html> on-line searched Mar. 15, 2004; and
Non-patent document 5: Oh-Bong Kwon et. al., “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640.times.480 CMOS Imaging System,” VL3-03 1999 IEEE p. 335-338.
The A/ID conversion mechanisms disclosed in these documents have difficulty in terms of the size and area of a circuit, power consumption, the number of interfacing lines with another functional block, noise picked up by the lines, and current consumption.
FIG. 6 illustrates a known CMOS solid-state image pickup device 1 (CMOS image sensor) having an A/D converter and a pixel area mounted on the same semiconductor substrate. As shown in FIG. 6, the solid-state image pickup device 1 includes a pixel array (image pickup area) 10 having a plurality of unit pixels 3 arranged in a matrix, a driver 7 arranged outside the pixel array 10, a counter (CNT) 24, a column processor 26 including a column A/D converter 25 arranged on a per column basis, a reference signal generator 27 including a DAC (digital-to-analog converter) for supplying a reference voltage for D/A conversion to the column A/D converter 25 in the column processor 26, and an output circuit 28 including a subtracter 29.
The driver 7 includes a horizontal (row) scanning circuit 12 for controlling column addresses and column scanning, a vertical (row) scanning circuit 14 for controlling row addresses and row scanning, and a timing controller 21 for receiving a master clock CLK0 via a terminal 5a, and for generating a variety of internal clocks to control the horizontal scanning circuit 12 and the vertical scanning circuit 14.
Each unit pixel 3 is connected to a row control line 15 controlled by the vertical scanning circuit 14 and a vertical signal line 19 for transferring a pixel signal to the column processor 26.
The column A/D converter 25 includes a voltage comparator 252 and a data memory 255. The voltage comparator 252 compares a reference voltage RAMP generated by the reference signal generator 27 with an analog pixel signal obtained via the vertical signal line 19 (V0, V1, . . . ) from the unit pixel 3 on a per row control line 15 (H0, H1, . . . ). The data memory 255 includes latches (flipflops) as a memory for storing a count of the counter 24 that counts time until the voltage comparator 252 completes the comparison process. The column A/D converter 25 has a function of n bit A/D conversion. The data memory 255 includes a latch 1 and a latch 2, each having n bit capacity, as an independent internal memory area.
The ramp reference voltage RAMP generated by the reference signal generator 27 is commonly fed to input RAMP terminals of the voltage comparators 252 while respective pixel signal voltages from the pixel array 10 are supplied to the other terminals of the voltage comparators 252 connected to the vertical signal lines 19 of the corresponding column lines. The output of the voltage comparator 252 is supplied to the data memory 255.
The counter 24 performs a count process in accordance with a count clock CLK0 corresponding to the master clock CK0 (both clocks having the same clock frequency). The counter 24 thus outputs count output CK1, CK2, . . . , CKn together with the count clock CK0 to each column A/D converter 25 in the column processor 26.
The lines for the count outputs CK1, CK2, . . . , CKn from the counter 24 are routed to the latches of the data memory 255 arranged for each column. The column A/D converter 25 thus operates commonly in response to the single counter 24.
The output of the column A/D converter 25 is connected to a horizontal signal line 18. The horizontal signal line 18 include signal lines covering 2n bit width, and is connected to the subtracter 29 in the output circuit 28 via 2n sense circuits (not shown) corresponding to the output lines of the horizontal signals of the horizontal signal line 18. Video data D1 output from the output circuit 28 is output to the outside via an output terminal 5c from the solid-state image pickup device 1.
FIG. 7 is a timing diagram illustrating operation of the solid-state image pickup device 1 of FIG. 6.
The count of the counter 24 is reset to an initial value “0” for a first reading operation. After the first reading from the unit pixel 3 of any row Hx to the vertical signal line 19 (V0, V1, . . . ) is stabilized, the reference voltage RAMP that is ramped in time axis by the reference signal generator 27 is input. The voltage comparator 252 compares the reference voltage RAMP with a pixel signal voltage of any vertical signal line 19 (column number Vx).
The counter 24 starts counting a conversion time of the voltage comparator 252 at the moment the reference voltage RAMP is inputted to the one terminal RAMP of each of the voltage comparator 252. In synchronization with the ramp waveform voltage issued from the reference signal generator 27 (time t10), the counter 24 starts down-counting from the initial value “0” in a first counting operation.
The voltage comparator 252 compares the ramp reference voltage RAMP from the reference signal generator 27 with a pixel signal voltage Vx input via the vertical signal line 19. When both voltages become equal to each other, the voltage comparator 252 inverts the comparator output from a high level to a low level (at time t12).
At about the same time as the inversion of the comparator output, the data memory 255 latches in the latch 1 thereof the count outputs CK1, CK2, . . . , CKn from the counter 24 in response to the comparison time in synchronization with the count clock CK0. A first conversion operation is thus complete (at time t12).
When a predetermined down-count period has elapsed (at time t14), the timing controller 21 stops supplying control data to the voltage comparator 252 and supplying the count clock CK0 to the counter 24. The voltage comparator 252 thus stops the comparison operation thereof.
During the first reading operation, a reset component .DELTA.V of the unit pixel 3 is read. The reset component .DELTA.V contains noise varying from unit pixel 3 to unit pixel 3 as an offset. The variations of the reset component .DELTA.V is typically small, and a reset level is common to all pixels. The output of any vertical signal line 19 (Vx) is largely known.
The comparison period during the first reading of the reset component .DELTA.V is shortened by adjusting the reference voltage RAMP. In this known example, the reset component .DELTA.V is adjusted within a count period of 7 bits (128 clocks).
In the second reading operation, a signal component Vsig responsive to an amount of incident light per unit pixel 3 is read in addition to the reset component .DELTA.V, and the same operation as in the first reading operation is performed.
The count of the counter 24 is reset to “0” for a second reading operation. After the second reading from the unit pixel 3 of any row Hx to the vertical signal line 19 (V0, V1, . . . ) is stabilized, the reference voltage RAMP that is ramped in time axis by the reference signal generator 27 is input. The voltage comparator 252 compares the reference voltage RAMP with a pixel signal voltage of any vertical signal line 19 (column number Vx).
The counter 24 starts counting a conversion time of the voltage comparator 252 at the moment the reference voltage RAMP is inputted to the one terminal RAMP of each of the voltage comparator 252. In synchronization with the ramp waveform voltage issued from the reference signal generator 27 (time t20), the counter 24 starts down-counting from the initial value “0” in a second counting operation.
The voltage comparator 252 compares the ramp reference voltage RAMP from the reference signal generator 27 with a pixel signal voltage Vx inputted via the vertical signal line 19. When both voltages become equal to each other, the voltage comparator 252 inverts the comparator output from a high level to a low level (at time t22).
At about the same time as the inversion of the comparator output, the data memory 255 latches the count outputs CK1, CK2, . . . , CKn from the counter 24 in response to the comparison time in synchronization with the count clock CK0. A second conversion operation is thus complete (at time t22).
The data memory 255 latches the first count and the second count in a different location thereof, i.e., the latch 2. During the second reading operation, the reset component .DELTA.V and the signal component Vsig of the unit pixel 3 are read.
When a predetermined down-count period has elapsed (time t24), the timing controller 21 stops supplying control data to the voltage comparator 252 and stops supplying the count clock CK0 to the counter 24. In this way, the voltage comparator 252 stops the comparison operation thereof.
At a predetermined timing (time t28) of the end of the second counting operation, the timing controller 21 instructs the horizontal scanning circuit 12 to read pixel data. In response, the horizontal scanning circuit 12 successively shifts a horizontal selection signal CH(i) to be supplied to the data memory 255 via a control line 12C.
The count stored in the data memory 255, namely, the digital pixel data of n bits for the first and second reading operations, is successively output to the subtracter 29 in the output circuit 28 outside the column processor 26.
The n-bit subtracter 29 subtracts the first pixel data representing the reset component .DELTA.V of the unit pixel 3 from the second pixel data as a sum of the reset component .DELTA.V and the signal component Vsig of the unit pixel 3 at each pixel position, thereby determining the signal component Vsig of the unit pixel 3.
The same operation is repeated. The output circuit 28 results in a video signal representing a two-dimensional image.
In the above-described known technique, the counter 24 is commonly used by the column A/D converters 25 of all columns. Each memory of the data memory 255 needs to store the first count and the second count. The data memory 255 uses a pair of n-bit latches for n bit signals (namely, 2n latches for each bit), thereby requiring a large circuit area. This problem is hereinafter referred to as a first problem.
Not only the line for the synchronization count clock CK0 but also the lines for the count outputs CK1, CK2, . . . , CKn from the counter 24 need to be routed to the latches 1 and 2 of the data memory 255. Because of this routing, an increase in noise and an increase in power consumption become a concern. This problem is hereinafter referred to as a second problem.
Since the first count and the second count are stored in the different locations in the data memory 255, 2n signal lines are required to transfer the count results to the data memory 255, and currents involved increase accordingly. This problem is hereinafter referred to as a third problem.
The output circuit 28 subtracts the first count from the second count prior to the signal output, and 2n signal lines for transferring the count to the n bit subtracter 29 in the output circuit 28 at each time are required. An increase in noise and an increase in power consumption due to data transfer become a concern. This problem is hereinafter referred to as a fourth problem.
A memory for storing the first read results and a memory storing the second read results need to be separately arranged in addition to the counter, in other words, two memories are required. Signal lines for transferring the n-bit count from the counter to the memories are required. Further, 2n bit signal lines for transferring the first count and the second count, each count being n bits, to the subtracter are also required. The circuit scale and the circuit area are increased, leading to increases in noise, current consumption and power consumption.
In a pipeline arrangement that permits the A/D conversion and the reading process to be performed in parallel, a memory for storing A/D converted data is required in addition to a memory for storing the count results. As in the first problem, two memory systems are required, leading to an increase in the circuit area. This problem is hereinafter referred to a fifth problem.
To overcome the first problem, the previously quoted non-patent document 2 has proposed a column A/D converter. The column A/D converter performs a correlated double sampling (CDS) function and an A/D conversion function by cascading a counter commonly used for vertical columns with a CDS processing unit and a latch for latching the count of the counter arranged for each column.
To overcome the second problem, the previously quoted patent document 1 and non-patent documents 3-5 have proposed an arrangement in which a counter is arranged on a per column basis in the column processor 26 to perform the A/D function.
An A/D converter disclosed in the non-patent document 2 includes a counter for performing a parallel process on the vertical signal lines (for the vertical columns) and an A/D circuit using a latch, and calculates a difference between a reset component and a signal component. The A/D converter thus converts the input signal into digital data while suppressing fixed pattern noise of the pixels. With this arrangement, no subtraction process is required, and a single count process is sufficient. The memory for storing A/D converted data is constructed of a latch, thereby avoiding an increase in circuit area. In other words, the first, third, fourth, and fifth problems are overcome.
Since the counter is commonly shared by all vertical column lines in the same way as show in FIG. 6, n lines for the count outputs CK1, CK2, . . . , CKn from the counter are needed. The second problem is not solved.
In accordance with the technique disclosed by the non-patent documents 3 and 4, currents from a plurality of pixels for detecting light are outputted to an output bus, and summing and subtraction operations are performed on the currents on the bus. The resulting signal is converted in a pulse-width signal having a length in time direction. The number of clocks responsive to the pulse width of the pulse-width signal are counted in counters arranged in parallel to perform A/D conversion. This arrangement eliminates the need for the wiring for the counter output. In other words, the second problem is solved.
However, there is no mention about the handling of a reset component and a signal component, and it is not certain that the technique disclosed in the non-patent documents 3 and 4 solves the first, third, fourth, and fifth problems. Likewise, the non-patent documents 1 and 5 also fail to state how a reset component and the signal component are handled.
In contrast, the patent document 1 discloses the manner of handling of a reset component and a signal component. Using a correlated double sampling unit, a subtraction process for subtracting digital data of the signal component from digital data of the reset component is performed every vertical column. Voltage data of pure image is thus extracted from the reset component and the signal component. The fourth problem is thus solved.
With the technique disclosed in the patent document 1, a count signal is generated in a count process by an external system interface. One pair of buffers arranged for each vertical column stores a count at the moment the voltage of one of a reset component and a signal component matches a reference voltage in a comparison process. The arrangement of the A/D conversion is identical to the technique disclosed in the non-patent document 1 in that a single counter is commonly shared by all vertical column lines. The first, second, third, and fifth problems remain unsolved.